Although applicable to any desired integrated circuits, in principle, the present invention and the problem area on which it is based are explained with regard to integrated circuits in silicon technology.
It is generally known that, in particular in semiconductor memory devices, such as e.g. DRAMs (Dynamic Random Access Memory), trenches are provided in order to form storage capacitors therein. Furthermore, trenches are generally required in integrated circuits in order to form an isolation between different components or component regions.
It is often necessary to produce trenches of different depth in a substrate. One possibility for producing such trenches of different depth consists in producing the trenches by means of different critical lithography steps.
However, this possibility has the crucial disadvantage that at least two critical lithography steps are required, which increases the susceptibility to faults and reduces the yield in the process. The critical lithography steps limit the throughput and are expensive. A reduction of costs is therefore sought.
Therefore, it is an object of the present invention to provide an improved fabrication method for a trench arrangement in a semiconductor substrate, whereby trenches of different depth can be fabricated more simply.
The idea on which the present invention is based consists in a region made of a material which has a reduced etching rate—compared with the semiconductor substrate—during the etching process being provided in specific mask openings above the semiconductor substrate.
A particular advantage of the present invention is that trenches of different depth can be produced in an integrated etching process step.
In accordance with one preferred development, the region is provided below a photoresist mask.
In accordance with a further preferred development, the region is provided within or below a hard mask.
In accordance with a further preferred development, the region is formed by a layer made of the material being deposited on the semiconductor substrate and subsequently being patterned photolithographically.
In accordance with a further preferred development, before the application of the mask, provision is made of a planarization layer for planarizing the semiconductor substrate with the region.
In accordance with a further preferred development, the planarization layer is an antireflection layer.
In accordance with a further preferred development, the region is provided as a remaining part of a hard mask, in which the second opening is not opened right through.
In accordance with a further preferred development, the etching process is a single-stage etching process.
In accordance with a further preferred development, the etching process is a two-stage etching process, the region forming an etching stop in a first selective etching stage and subsequently being removed in a second non-selective etching stage.
In accordance with a further preferred development, an additional etching stop layer is provided on the entire surface of the semiconductor substrate, which layer forms an etching stop in the first opening in the first selective etching stage and is subsequently removed in the second non-selective etching stage.
Exemplary embodiments of the invention are illustrated in the drawings and are explained in more detail in the description below.
In the figures, identical reference symbols designate identical or functionally identical constituent parts.